rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3335 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000 high accuracy ultralow i q , 500 ma anycap low dropout regulator functional block diagram thermal protection cc in adp3335 out r1 r2 gnd q1 sd bandgap ref driver g m nr features high accuracy over line and load: 0.9% @ 25 c, 1.8% over temperature ultralow dropout voltage: 200 mv (typ) @ 500 ma requires only c o = 1.0 f for stability anycap = stable with any type of capacitor (including mlcc) current and thermal limiting low noise low shutdown current: < 1.0 a 2.6 v to 12 v supply range ?0 c to +85 c ambient temperature range ultrasmall thermally-enhanced 8-lead msop package applications pcmcia card cellular phones camcorders, cameras networking systems, dsl/cable modems cable set-top box mp3/cd players dsp supply anycap is a registered trademark of analog devices inc. v out adp3335 nr out on off sd gnd c out 1 f + out out c in 1 f + v in in in figure 1. typical application circuit general description the adp3335 is a member of the adp330x family of precision low dropout anycap voltage regulators. the adp3335 operates with an input voltage range of 2.6 v to 12 v and delivers a con- tinuous load current up to 500 ma. the adp3335 stands out from conventional ldos with the lowest thermal resistance of any msop-8 package and an enhanced process that enables it to offer performance advantages beyond its competition. its patented design requires only a 1.0 f output capacitor for sta- bility. this device is insensitive to output capacitor equivalent series resistance (esr), and is stable with any good quality capacitor, including ceramic (mlcc) types for space-restricted applications. the adp3335 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. the dropout voltage of the adp3335 is only 200 mv (typical) at 500 ma. this device also includes a safety current limit, thermal overload protection and a shutdown feature. in shutdown mode, the ground current is reduced to less than 1 a. the adp3335 has ultralow quiescent current 80 a (typical) in light load situations.
? rev. 0 adp3335?pecifications 1, 2, 3 (v in = 6.0 v, c in = c out = 1.0 f, t a = ?0 c to +85 c, unless otherwise noted) parameter symbol conditions min typ max unit output voltage accuracy 4 v out v in = v out(nom) + 0.4 v to 12 v ?.9 +0.9 % i l = 0.1 ma to 500 ma t a = 25 c v in = v out(nom) + 0.4 v to 12 v ?.8 +1.8 % i l = 0.1 ma to 500 ma t a = 85 c v in = v out(nom) + 0.4 v to 12 v ?.3 +2.3 % i l = 0.1 ma to 500 ma t j = 150 c line regulation 4 v in = v out(nom) + 0.4 v to 12 v 0.04 mv/v i l = 0.1 ma t a = 25 c load regulation i l = 0.1 ma to 500 ma 0.04 mv/ma t a = 25 c dropout voltage v drop v out = 98% of v out(nom) i l = 500 ma 200 370 mv i l = 300 ma 140 230 mv i l = 50 ma 30 110 mv i l = 0.1 ma 10 40 mv peak load current i ldpk v in = v out(nom) + 1 v 800 ma output noise v noise f = 10 hz?00 khz, c l = 10 f47 v rms i l = 500 ma, c nr = 10 nf f = 10 hz?00 khz, c l = 10 f95 v rms i l = 500 ma, c nr = 0 nf ground current in regulation i gnd i l = 500 ma 4.5 10 ma i l = 300 ma 2.6 6 ma i l = 50 ma 0.5 2.5 ma i l = 0.1 ma 80 110 a in dropout i gnd v in = v out(nom) ?100 mv 120 400 a i l = 0.1 ma in shutdown i gndsd sd = 0 v, v in = 12 v 0.01 1 a shutdown threshold voltage v thsd on 2.0 v off 0.4 v sd input current i sd 0 sd 5 v 1.2 3 a output current in shutdown i osd t a = 25 c, v in = 12 v 1.2 5 a t a = 85 c, v in = 12 v 1.2 5 a notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 ambient temperature of 85 c corresponds to a junction temperature of 125 c under pulsed full load test conditions. 3 application stable with no load. 4 v in = 2.6 v to 12 v for models with v out(nom) 2.2 v. specifications subject to change without notice.
adp3335 ? rev. 0 absolute maximum ratings * input supply voltage . . . . . . . . . . . . . . . . . . . ?.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . ?.3 v to +16 v power dissipation . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . . ?0 c to +85 c operating junction temperature range . . . ?0 c to +150 c ja 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 c/w ja 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 c/w storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . 300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. pin function descriptions pin no. mnemonic function 1, 2, 3 out output of the regulator. bypass to ground with a 1.0 f or larger capacitor. all pins must be connected together for proper operation. 4 gnd ground pin. 5 nr noise reduction pin. used for further reduction of output noise (see text for detail). capacitor required if c out > 3.3 f. 6 sd active low shutdown pin. connect to ground to disable the regulator output. when shutdown is not used, this pin should be connected to the input pin. 7, 8 in regulator input. all pins must be con- nected together for proper operation. pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 sd in in out adp3335 nr out out gnd ordering guide output package branding model voltage * option information adp3335arm-1.8 1.8 v rm-8 (msop-8) lfa adp3335arm-2.5 2.5 v rm-8 (msop-8) lfc adp3335arm-2.85 2.85 v rm-8 (msop-8) lfd adp3335arm-3.3 3.3 v rm-8 (msop-8) lfe adp3335arm-5 5 v rm-8 (msop-8) lff * contact the factory for other output voltage options. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3335 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
adp3335 ? rev. 0 input voltage ?volts output voltage ?volts 2.202 2.201 2.194 24 12 6810 2.198 2.197 2.196 2.195 2.200 2.199 i l = 0 v out = 2.2v 500ma 150ma 300ma figure 2. line regulation output voltage vs. supply voltage output load ma ground current ma 5.0 0 0 100 500 200 300 400 2.0 1.0 4.0 3.0 figure 5. ground current vs. load current output load ma dropout voltage mv 250 200 0 0 100 500 200 300 400 150 100 50 figure 8. dropout voltage vs. output current typical performance characteristics output load ma output voltage volts 2.201 2.200 2.193 0 100 500 200 300 400 2.197 2.196 2.195 2.194 2.199 2.198 v out = 2.2v v in = 6v figure 3. output voltage vs. load current junction temperature c output change % 1 0.5 40 105 15 5 25 45 65 85 0.6 0.9 0.8 0.7 125 0 0.2 0.1 0.4 0.3 0.2 0.3 0.1 0.4 500ma 0 300ma 0 500ma figure 6. output voltage variation % vs. junction temperature time sec input/output voltage volts 0 0.5 1.0 1.5 2.0 2.5 3.0 1234 v out = 2.2v sd = v in r l = 4.4 figure 9. power-up/power-down input voltage volts ground current a 140 60 0 0 12 24 68 10 120 100 40 20 80 v out = 2.2v i l = 100 a i l = 0 figure 4. ground current vs. supply voltage junction temperature c ground current ma 8 6 40 105 155 25456585 7 125 5 3 4 1 2 0 300ma 0 100ma i l = 500ma 50ma figure 7. ground current vs. junction temperature time s 0 2 4 0 1 2 3 200 v out = 2.2v sd = v in r l = 4.4 v in volts v out volts c out = 10 f c out = 1 f 400 600 800 figure 10. power?p response (t a = 25 c unless otherwise noted.)
adp3335 ? rev. 0 v out = 2.2v r l = 4.4 c l = 1 f time s 3.000 3.500 2.179 2.189 2.190 2.200 2.210 40 80 140 180 v in volts v out volts figure 11. line transient response v out = 2.2v r l = 4.4 c l = 10 f time s 0 200 400 2.1 2.2 2.3 200 400 600 800 ma volts figure 14. load transient response frequency hz ripple rejection db 10 100 1k 10k 100k 1m 10m 20 30 40 50 60 70 80 90 c l = 1 f i l = 500ma c l = 1 f i l = 50 a c l = 10 f i l = 500ma c l = 10 f i l = 50 a v out = 2.2v figure 17. power supply ripple rejection v out = 2.2v r l = 4.4 c l = 10 f time s 3.000 3.500 2.179 2.189 2.190 2.200 2.210 40 80 140 180 v in volts v out volts figure 12. line transient response time s 0 1 2 0 2.2 200 400 600 800 a volts v in = 4v 800m short full short 3 figure 15. short circuit current 120 160 050 10 20 30 40 100 80 60 140 c l f rms noise v 40 20 0 c nr = 10nf i l = 0ma with noise reduction i l = 0ma without noise reduction i l = 500ma without noise reduction i l = 500ma with noise reduction figure 18. rms noise vs. c l (10 hz?00 khz) v in = 4v v out = 2.2 c l = 1 f time s 200 400 600 800 0 200 400 2.1 2.2 2.3 ma volts figure 13. load transient response time s 0 2 0 1 200 400 600 800 v sd 10 f v out 2 3 v in = 6v v out = 2.2v r l = 4.4 1 f 10 f 1 f figure 16. turn on?urn off response frequency hz voltage noise spectral density v/ hz 100 10 100 1m 1k 10k 100k 10 1 0.1 0.01 0.001 v out = 2.2v i l = 1ma c l = 1 f c nr = 0 c l = 10 f c nr = 0 c l = 1 f c nr = 10nf c l = 10 f c nr = 10nf figure 19. output noise density
adp3335 ? rev. 0 theory of operation the new anycap ldo adp3335 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 which is varied to provide the available output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. ptat v os g m noninverting wideband driver input q1 adp3335 compensation capacitor attenuation (v bandgap /v out ) r1 d1 r2 r3 r4 output ptat current (a) gnd c load r load figure 20. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that equilibrium pro- duces a large, temperature-proportional input ,?ffset voltage that is repeatable and very well controlled. the temperature- propo rtional offset voltage is combined with the complementary diode voltage to form a ?irtual bandgap?voltage, implicit in the network, although it never appears explicitly in the circuit. ultim ately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the n oise characteristics of the amplifier by pro viding more flex- ibil ity on the trade-off of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the bandgap voltage to the output volt age. although the r1, r2 resistor divider is loaded by the diode d1 and a second divider consisting of r3 and r4, the values can be chosen to produce a temperature stable output. this unique arrangement specifically corrects for the load- ing of the divider thus avoiding the error resulting from base current loading in conventional circuits. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this spe- cial noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. more- over, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. t hese esr limita- tions make designing with ldos more difficult because of their unclear specifications and extreme varia tions over temperature. with the adp3335 anycap ldo, this is no longer true. it can be used with virtually any good quality capacitor, with no con- straint on the minimum esr. this innovative design allows the circuit to be stable with just a small 1 f capacitor on the out- put. additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. an impressive 1.8% accuracy is guaranteed over line, load, and temperature. additional features of the circuit include current limit and ther- mal shutdown and noise reduction. application information capacitor selection output capacitors: as with any micropower device, output transient response is a function of the output capacitance. the adp3335 is stable with a wide range of capacitor values, types and esr (anycap). a capacitor as low as 1 f is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. the adp3335 is stable with extremely low esr capacitors (esr 0), such as multilayer ceramic capacitors (mlcc) or oscon. note that the effective capacitance of some capacitor types may fall below the mini- mum at cold temperature. ensure that the capacitor pro vides more than 1 f at minimum temperature. input bypass capacitor an input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. connecting a 1 f capacitor from in to ground reduces the circuit's sensitivity to pc board layout. if a larger value output capacitor is used, then a larger value input capaci- tor is also recommended. noise reduction a noise reduction capacitor (c nr ) can be used to further reduce the noise by 6 db?0 db (figure 18) low leakage capacitors in 10 pf?00 pf range provide the best performance. since the noise reduction pin (nr) is internally connected to a high imped- ance node, any connection to this node should be carefully done to avoid noise pickup from external sources. the pad conne cted to this pin should be as small as possible and long pc board traces are not recommended. when adding a noise reduction capacitor, maintain a mini- mum load current of 1 ma when not in shutdown.
adp3335 ? rev. 0 it is important to note that as c nr increases, the turn-on time will be delayed. with nr values greater than 1 nf, this delay may be on the order of several milliseconds. v in v out adp3335 on off sd gnd c out 1 f + nr c nr out out out in in c in 1 f + figure 21. typical application circuit paddle-under-lead package the adp3335 uses a patented paddle-under-lead package design to ensure the best thermal performance in an msop-8 footprint. t his new package uses an electrically isolated die attach that allows all pins to contribute to heat conduction. this technique reduces the thermal resistance to 110 c/w on a 4-layer board as compared to >160 c/w for a standard msop-8 leadframe. figure 22 shows the standard physical construc- tion of the msop-8 and the paddle-under-lead leadframe. die figure 22. thermally enhanced paddle-under-lead package thermal overload protection the adp3335 is protected against damage from exce ssive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of 165 c. under extreme conditions (i.e., high a mbient tempera ture and power dissipa tion) where die temperature starts to rise above 165 c, the output current is reduced until the die temperature has dropped to a safe level. the output current is restored when the die tempera- ture is reduced. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150 c. calculating junction temperature device power dissipation is calculated as follows: pvvi vi d in out load in gnd =? () + () where i load and i gnd are load current and ground current, v in and v out are input and output voltages respectively. assuming i load = 400 ma, i gnd = 4 ma, v in = 5.0 v and v out = 3.3 v, device power dissipation is: p d = (5 ?3.3) 400 ma + 5.0(4 ma ) = 700 mw the proprietary package used in the adp3335 has a thermal resistance of 110 c/w, significantly lower than a standard msop-8 package. assuming a 4-layer board, the junction tem- perature rise above ambient temperature will be approximately equal to: ? twcwc a j == 0 700 110 77 0 ./. to limit the maximum junction temperature to 150 c, maxi- mum allowable ambient temperature will be: t amax = 150 c 77.0 c = 73.0 c printed circuit board layout consideration all surface mount packages rely on the traces of the pc board to conduct heat away from the package. in standard packages the dominant component of the heat resis- tance path is the plastic between the die attach pad and the individual leads. in typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. to make the improvement mean- ingful, however, a significant copper area on the pcb must be attached to these fused pins. the patented paddle-un der-lead frame design of the adp3335 uniformly minimizes the value of the dominant portion of the thermal resistance. it ensures that heat is conducted away by all pins of the package. this yields a very low 110 c/w thermal resistance for an msop-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. this yields a 33% improvement in heat dissipation capability as compared to a standard msop-8 package. the thermal resistance can be decreased by, approximately, an addi- tional 10% by attaching a few square cm of copper area to the in pin of the adp3335 package. it is not recommended to use solder mask or silkscreen on the pcb traces adjacent to the adp3335 s pins since it will increase the junction-to-ambient thermal resistance of the package. shutdown mode applying a ttl high signal to the shutdown ( sd ) pin or tying it to the input pin, will turn the output on. pulling sd down to 0.4 v or below, or tying it to ground will turn the output off. in shutdown mode, quiescent current is reduced to much less than 1 a.
? c3774??/00 (rev. 0) printed in u.s.a. adp3335 rev. 0 outline dimensions dimensions shown in inches and (mm). 8-lead mini_so (rm-8) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84)
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